//#include "cmd.h"
//#include "simple_dma.h"
//
//uint8_t rxflag=0;
//uint8_t flag_tcp=0;
//uint8_t flag_1x=0;
//int Simple1xDmaInit()
//{
//	int Status;
//	XAxiDma_Config *Config;
//
//	CmdRxBufferPtr_1x = (u8 *)(RX_BUFFER_BASE+0x6000);
//
//	Config = XAxiDma_LookupConfig(DMA_DEV_ID);
//	if (!Config) {
//		xil_printf("No config found for %d\r\n", DMA_DEV_ID);
//		return XST_FAILURE;
//	}
//	xil_printf("%s %d\n", __FUNCTION__, __LINE__);
//	/* Initialize DMA engine */
//	Status = XAxiDma_CfgInitialize(&AxiDma, Config);
//
//	if (Status != XST_SUCCESS) {
//		xil_printf("Initialization failed %d\r\n", Status);
//		return XST_FAILURE;
//	}
//
//	if(XAxiDma_HasSg(&AxiDma)) {
//		xil_printf("Device configured as SG mode \r\n");
//		return XST_FAILURE;
//	}
//
//	/* Disable all interrupts before setup */
//
//	XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
//						XAXIDMA_DMA_TO_DEVICE);
//
//	XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
//				XAXIDMA_DEVICE_TO_DMA);
//
//	/* Initialize flags before start transfer test  */
//	TxDone = 0;
//	RxDone = 0;
//	Error = 0;
//
//	Xil_DCacheFlushRange((UINTPTR)CmdRxBufferPtr_1x, 0x10);
//
//	Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) CmdRxBufferPtr_1x,
//				0x4, XAXIDMA_DEVICE_TO_DMA);
//	if (Status != XST_SUCCESS) {
//		return XST_FAILURE;
//	}
//	return 0;
//}
//
//int SimpleTcpDmaInit()
//{
//	int Status;
//	XAxiDma_Config *Config;
//
//	CmdTxBufferPtr = (u8 *)TX_BUFFER_BASE;
//	CmdRxBufferPtr = (u8 *)RX_BUFFER_BASE;
//
//	Config = XAxiDma_LookupConfig(DMA_DEV_ID2);
//	if (!Config) {
//		xil_printf("No config found for %d\r\n", DMA_DEV_ID2);
//		return XST_FAILURE;
//	}
//	xil_printf("%s %d\n", __FUNCTION__, __LINE__);
//	/* Initialize DMA engine */
//	Status = XAxiDma_CfgInitialize(&AxiDma1, Config);
//
//	if (Status != XST_SUCCESS) {
//		xil_printf("Initialization failed %d\r\n", Status);
//		return XST_FAILURE;
//	}
//
//	if(XAxiDma_HasSg(&AxiDma1)) {
//		xil_printf("Device configured as SG mode \r\n");
//		return XST_FAILURE;
//	}
//
//	/* Set up Interrupt system  */
//	Status = SetupIntrSystem(&Intc, &AxiDma1, TX_INTR_ID2, RX_INTR_ID2);
//	if (Status != XST_SUCCESS) {
//
//		xil_printf("Failed intr setup\r\n");
//		return XST_FAILURE;
//	}
//
//	/* Disable all interrupts before setup */
//
//	XAxiDma_IntrDisable(&AxiDma1, XAXIDMA_IRQ_ALL_MASK,
//						XAXIDMA_DMA_TO_DEVICE);
//
//	XAxiDma_IntrDisable(&AxiDma1, XAXIDMA_IRQ_ALL_MASK,
//				XAXIDMA_DEVICE_TO_DMA);
//
//	/* Enable all interrupts */
////	XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
////							XAXIDMA_DMA_TO_DEVICE);
//
//	XAxiDma_IntrEnable(&AxiDma1, XAXIDMA_IRQ_ALL_MASK,
//							XAXIDMA_DEVICE_TO_DMA);
//
//	/* Initialize flags before start transfer test  */
//	TxDone = 0;
//	RxDone = 0;
//	Error = 0;
//
//	Xil_DCacheFlushRange((UINTPTR)CmdRxBufferPtr, MAX_PKT_LEN);
//
//	Status = XAxiDma_SimpleTransfer(&AxiDma1,(UINTPTR) CmdRxBufferPtr,
//				MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);
//	if (Status != XST_SUCCESS) {
//		return XST_FAILURE;
//	}
//	return 0;
//}
//
//
//
///*****************************************************************************/
///*
//*
//* This is the DMA TX Interrupt handler function.
//*
//* It gets the interrupt status from the hardware, acknowledges it, and if any
//* error happens, it resets the hardware. Otherwise, if a completion interrupt
//* is present, then sets the TxDone.flag
//*
//* @param	Callback is a pointer to TX channel of the DMA engine.
//*
//* @return	None.
//*
//* @note		None.
//*
//******************************************************************************/
//void TxIntrHandler(void *Callback)
//{
//
//	u32 IrqStatus;
//	int TimeOut;
//	XAxiDma *AxiDmaInst = (XAxiDma *)Callback;
//	xil_printf("--- into simple dma Tx handler --- \r\n");
//	/* Read pending interrupts */
//	IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DMA_TO_DEVICE);
//
//	/* Acknowledge pending interrupts */
//
//
//	XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DMA_TO_DEVICE);
//
//	/*
//	 * If no interrupt is asserted, we do not do anything
//	 */
//	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
//
//		return;
//	}
//
//	/*
//	 * If error interrupt is asserted, raise error flag, reset the
//	 * hardware to recover from the error, and return with no further
//	 * processing.
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
//
//		Error = 1;
//
//		/*
//		 * Reset should never fail for transmit channel
//		 */
//		XAxiDma_Reset(AxiDmaInst);
//
//		TimeOut = RESET_TIMEOUT_COUNTER;
//
//		while (TimeOut) {
//			if (XAxiDma_ResetIsDone(AxiDmaInst)) {
//				break;
//			}
//
//			TimeOut -= 1;
//		}
//
//		return;
//	}
//
//	/*
//	 * If Completion interrupt is asserted, then set the TxDone flag
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
//
//		TxDone = 1;
//	}
//}
//
//void TxIntrHandler1(void *Callback)
//{
//
//	u32 IrqStatus;
//	int TimeOut;
//	XAxiDma *AxiDmaInst = (XAxiDma *)Callback;
//	xil_printf("--- into simple tcp dma Tx handler --- \r\n");
//	/* Read pending interrupts */
//	IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DMA_TO_DEVICE);
//
//	/* Acknowledge pending interrupts */
//
//
//	XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DMA_TO_DEVICE);
//
//	/*
//	 * If no interrupt is asserted, we do not do anything
//	 */
//	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
//
//		return;
//	}
//
//	/*
//	 * If error interrupt is asserted, raise error flag, reset the
//	 * hardware to recover from the error, and return with no further
//	 * processing.
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
//
//		Error = 1;
//
//		/*
//		 * Reset should never fail for transmit channel
//		 */
//		XAxiDma_Reset(AxiDmaInst);
//
//		TimeOut = RESET_TIMEOUT_COUNTER;
//
//		while (TimeOut) {
//			if (XAxiDma_ResetIsDone(AxiDmaInst)) {
//				break;
//			}
//
//			TimeOut -= 1;
//		}
//
//		return;
//	}
//
//	/*
//	 * If Completion interrupt is asserted, then set the TxDone flag
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
//
//		TxDone = 1;
//	}
//}
///*****************************************************************************/
///*
//*
//* This is the DMA RX interrupt handler function
//*
//* It gets the interrupt status from the hardware, acknowledges it, and if any
//* error happens, it resets the hardware. Otherwise, if a completion interrupt
//* is present, then it sets the RxDone flag.
//*
//* @param	Callback is a pointer to RX channel of the DMA engine.
//*
//* @return	None.
//*
//* @note		None.
//*
//******************************************************************************/
//void RxIntrHandler(void *Callback)
//{
//	u32 IrqStatus;
//	int TimeOut,Status;
//	XAxiDma *AxiDmaInst = (XAxiDma *)Callback;
//	xil_printf("--- into simple 1x dma Rx handler --- \r\n");
//	/* Read pending interrupts */
//	IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DEVICE_TO_DMA);
//
//	/* Acknowledge pending interrupts */
//	XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DEVICE_TO_DMA);
//
//	/*
//	 * If no interrupt is asserted, we do not do anything
//	 */
//	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
//		return;
//	}
//
//	/*
//	 * If error interrupt is asserted, raise error flag, reset the
//	 * hardware to recover from the error, and return with no further
//	 * processing.
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
//
//		Error = 1;
//
//		/* Reset could fail and hang
//		 * NEED a way to handle this or do not call it??
//		 */
//		XAxiDma_Reset(AxiDmaInst);
//
//		TimeOut = RESET_TIMEOUT_COUNTER;
//
//		while (TimeOut) {
//			if(XAxiDma_ResetIsDone(AxiDmaInst)) {
//				break;
//			}
//
//			TimeOut -= 1;
//		}
//		return;
//	}
//
//	/*
//	 * If completion interrupt is asserted, then set RxDone flag
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
//
//		RxDone = 1;
//	}
//	xil_printf("--- begin parsing of cmd --- \r\n");
//	cmd_parse();//parse recv cmd from uper   //wfeng
//	flag_1x=1;
////	rxflag=1;
//	xil_printf("--- cmd_parse complete --- \r\n");
//	//rx re enable
//	Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR)CmdRxBufferPtr,
//			MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);   // 1.5 �� by lyh  MAX_PKT_LEN�ĳ�6169
//	if (Status != XST_SUCCESS) {
//		return XST_FAILURE;
//	}
//
//}
//
//void RxIntrHandler1(void *Callback)
//{
//	u32 IrqStatus;
//	int TimeOut,Status;
//	XAxiDma *AxiDmaInst = (XAxiDma *)Callback;
//	xil_printf("--- into simple tcp dma Rx handler --- \r\n");
//	/* Read pending interrupts */
//	IrqStatus = XAxiDma_IntrGetIrq(AxiDmaInst, XAXIDMA_DEVICE_TO_DMA);
//
//	/* Acknowledge pending interrupts */
//	XAxiDma_IntrAckIrq(AxiDmaInst, IrqStatus, XAXIDMA_DEVICE_TO_DMA);
//
//	/*
//	 * If no interrupt is asserted, we do not do anything
//	 */
//	if (!(IrqStatus & XAXIDMA_IRQ_ALL_MASK)) {
//		return;
//	}
//
//	/*
//	 * If error interrupt is asserted, raise error flag, reset the
//	 * hardware to recover from the error, and return with no further
//	 * processing.
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_ERROR_MASK)) {
//
//		Error = 1;
//
//		/* Reset could fail and hang
//		 * NEED a way to handle this or do not call it??
//		 */
//		XAxiDma_Reset(AxiDmaInst);
//
//		TimeOut = RESET_TIMEOUT_COUNTER;
//
//		while (TimeOut) {
//			if(XAxiDma_ResetIsDone(AxiDmaInst)) {
//				break;
//			}
//
//			TimeOut -= 1;
//		}
//		return;
//	}
//
//	/*
//	 * If completion interrupt is asserted, then set RxDone flag
//	 */
//	if ((IrqStatus & XAXIDMA_IRQ_IOC_MASK)) {
//
//		RxDone = 1;
//	}
//	xil_printf("--- begin parsing of cmd --- \r\n");
//	cmd_parse();//parse recv cmd from uper   //wfeng
//	flag_tcp=1;
////	rxflag=1;
//	xil_printf("--- cmd_parse complete --- \r\n");
//	//rx re enable
//	Status = XAxiDma_SimpleTransfer(&AxiDma1,(UINTPTR)CmdRxBufferPtr,
//			MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);   // 1.5 �� by lyh  MAX_PKT_LEN�ĳ�6169
//	if (Status != XST_SUCCESS) {
//		return XST_FAILURE;
//	}
//
//}
//
///*****************************************************************************/
///*
//*
//* This function setups the interrupt system so interrupts can occur for the
//* DMA, it assumes INTC component exists in the hardware system.
//*
//* @param	IntcInstancePtr is a pointer to the instance of the INTC.
//* @param	AxiDmaPtr is a pointer to the instance of the DMA engine
//* @param	TxIntrId is the TX channel Interrupt ID.
//* @param	RxIntrId is the RX channel Interrupt ID.
//*
//* @return
//*		- XST_SUCCESS if successful,
//*		- XST_FAILURE.if not succesful
//*
//* @note		None.
//*
//******************************************************************************/
////int SetupIntrSystem(INTC * IntcInstancePtr,
////			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId,XAxiDma * AxiDmaPtr1, u16 TxIntrId1, u16 RxIntrId1)
////{
////	int Status;
////
////#ifdef XPAR_INTC_0_DEVICE_ID
////
////	/* Initialize the interrupt controller and connect the ISRs */
////	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
////	if (Status != XST_SUCCESS) {
////
////		xil_printf("Failed init intc\r\n");
////		return XST_FAILURE;
////	}
////
////	Status = XIntc_Connect(IntcInstancePtr, TxIntrId,
////			       (XInterruptHandler) TxIntrHandler, AxiDmaPtr);
////	if (Status != XST_SUCCESS) {
////
////		xil_printf("Failed tx connect intc\r\n");
////		return XST_FAILURE;
////	}
////
////	Status = XIntc_Connect(IntcInstancePtr, RxIntrId,
////			       (XInterruptHandler) RxIntrHandler, AxiDmaPtr);
////	if (Status != XST_SUCCESS) {
////
////		xil_printf("Failed rx connect intc\r\n");
////		return XST_FAILURE;
////	}
////
////	Status = XIntc_Connect(IntcInstancePtr, TxIntrId1,
////			       (XInterruptHandler) TxIntrHandler, AxiDmaPtr1);
////	if (Status != XST_SUCCESS) {
////
////		xil_printf("Failed rx connect intc\r\n");
////		return XST_FAILURE;
////	}
////
////	Status = XIntc_Connect(IntcInstancePtr, RxIntrId1,
////			       (XInterruptHandler) RxIntrHandler, AxiDmaPtr1);
////	if (Status != XST_SUCCESS) {
////
////		xil_printf("Failed rx connect intc\r\n");
////		return XST_FAILURE;
////	}
////	/* Start the interrupt controller */
////	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
////	if (Status != XST_SUCCESS) {
////
////		xil_printf("Failed to start intc\r\n");
////		return XST_FAILURE;
////	}
////
////	XIntc_Enable(IntcInstancePtr, TxIntrId);
////	XIntc_Enable(IntcInstancePtr, RxIntrId);
////
////	XIntc_Enable(IntcInstancePtr, TxIntrId1);
////	XIntc_Enable(IntcInstancePtr, RxIntrId1);
////
////#else
////
////	XScuGic_Config *IntcConfig;
////
////
////	/*
////	 * Initialize the interrupt controller driver so that it is ready to
////	 * use.
////	 */
////	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
////	if (NULL == IntcConfig) {
////		return XST_FAILURE;
////	}
////
////	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
////					IntcConfig->CpuBaseAddress);
////	if (Status != XST_SUCCESS) {
////		return XST_FAILURE;
////	}
////
////
////	XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
////
////	XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3);
////	/*
////	 * Connect the device driver handler that will be called when an
////	 * interrupt for the device occurs, the handler defined above performs
////	 * the specific interrupt processing for the device.
////	 */
////	Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,
////				(Xil_InterruptHandler)TxIntrHandler,
////				AxiDmaPtr);
////	if (Status != XST_SUCCESS) {
////		return Status;
////	}
////
////	Status = XScuGic_Connect(IntcInstancePtr, RxIntrId,
////				(Xil_InterruptHandler)RxIntrHandler,
////				AxiDmaPtr);
////	if (Status != XST_SUCCESS) {
////		return Status;
////	}
////
////	XScuGic_Enable(IntcInstancePtr, TxIntrId);
////	XScuGic_Enable(IntcInstancePtr, RxIntrId);
////
////
////#endif
////
////	/* Enable interrupts from the hardware */
////
////	Xil_ExceptionInit();
////	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
////			(Xil_ExceptionHandler)INTC_HANDLER,
////			(void *)IntcInstancePtr);
////
////	Xil_ExceptionEnable();
////
////	return XST_SUCCESS;
////}
//int SetupIntrSystem(INTC * IntcInstancePtr,
//			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId)
//{
//	int Status;
//
//#ifdef XPAR_INTC_0_DEVICE_ID
//
//	/* Initialize the interrupt controller and connect the ISRs */
////	do
////	{
////		Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
////		if (Status != XST_SUCCESS) {
////
////			xil_printf("Failed init intc\r\n");
////			return XST_FAILURE;
////		}
////		usleep(100000);
////	} while(Status != XST_SUCCESS);
//
//	Status = XIntc_Connect(IntcInstancePtr, TxIntrId,
//			       (XInterruptHandler) TxIntrHandler1, AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//
//		xil_printf("Failed tx connect intc\r\n");
//		return XST_FAILURE;
//	}
//
//	Status = XIntc_Connect(IntcInstancePtr, RxIntrId,
//			       (XInterruptHandler) RxIntrHandler1, AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//
//		xil_printf("Failed rx connect intc\r\n");
//		return XST_FAILURE;
//	}
//
//	/* Start the interrupt controller */
//	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
//	if (Status != XST_SUCCESS) {
//
//		xil_printf("Failed to start intc\r\n");
//		return XST_FAILURE;
//	}
//
//	XIntc_Enable(IntcInstancePtr, TxIntrId);
//	XIntc_Enable(IntcInstancePtr, RxIntrId);
//
//#else
//
//	XScuGic_Config *IntcConfig;
//
//
//	/*
//	 * Initialize the interrupt controller driver so that it is ready to
//	 * use.
//	 */
//	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
//	if (NULL == IntcConfig) {
//		return XST_FAILURE;
//	}
//
//	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
//					IntcConfig->CpuBaseAddress);
//	if (Status != XST_SUCCESS) {
//		return XST_FAILURE;
//	}
//
//
//	XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
//
//	XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3);
//	/*
//	 * Connect the device driver handler that will be called when an
//	 * interrupt for the device occurs, the handler defined above performs
//	 * the specific interrupt processing for the device.
//	 */
//	Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,
//				(Xil_InterruptHandler)TxIntrHandler,
//				AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//		return Status;
//	}
//
//	Status = XScuGic_Connect(IntcInstancePtr, RxIntrId,
//				(Xil_InterruptHandler)RxIntrHandler,
//				AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//		return Status;
//	}
//
//	XScuGic_Enable(IntcInstancePtr, TxIntrId);
//	XScuGic_Enable(IntcInstancePtr, RxIntrId);
//
//
//#endif
//
//	/* Enable interrupts from the hardware */
//
//	Xil_ExceptionInit();
//	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
//			(Xil_ExceptionHandler)INTC_HANDLER,
//			(void *)IntcInstancePtr);
//
//	Xil_ExceptionEnable();
//
//	return XST_SUCCESS;
//}
//
//int SetupIntrSystem1(INTC * IntcInstancePtr,
//			   XAxiDma * AxiDmaPtr, u16 TxIntrId, u16 RxIntrId)
//{
//	int Status;
//
//#ifdef XPAR_INTC_0_DEVICE_ID
//
//	/* Initialize the interrupt controller and connect the ISRs */
////	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
////	if (Status != XST_SUCCESS) {
////
////		xil_printf("Failed init intc\r\n");
////		return XST_FAILURE;
////	}
//
//	Status = XIntc_Connect(IntcInstancePtr, TxIntrId,
//			       (XInterruptHandler) TxIntrHandler, AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//
//		xil_printf("Failed tx connect intc\r\n");
//		return XST_FAILURE;
//	}
//
//	Status = XIntc_Connect(IntcInstancePtr, RxIntrId,
//			       (XInterruptHandler) RxIntrHandler, AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//
//		xil_printf("Failed rx connect intc\r\n");
//		return XST_FAILURE;
//	}
//
//	/* Start the interrupt controller */
//	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
//	if (Status != XST_SUCCESS) {
//
//		xil_printf("Failed to start intc\r\n");
//		return XST_FAILURE;
//	}
//
//	XIntc_Enable(IntcInstancePtr, TxIntrId);
//	XIntc_Enable(IntcInstancePtr, RxIntrId);
//
//#else
//
//	XScuGic_Config *IntcConfig;
//
//
//	/*
//	 * Initialize the interrupt controller driver so that it is ready to
//	 * use.
//	 */
//	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
//	if (NULL == IntcConfig) {
//		return XST_FAILURE;
//	}
//
//	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
//					IntcConfig->CpuBaseAddress);
//	if (Status != XST_SUCCESS) {
//		return XST_FAILURE;
//	}
//
//
//	XScuGic_SetPriorityTriggerType(IntcInstancePtr, TxIntrId, 0xA0, 0x3);
//
//	XScuGic_SetPriorityTriggerType(IntcInstancePtr, RxIntrId, 0xA0, 0x3);
//	/*
//	 * Connect the device driver handler that will be called when an
//	 * interrupt for the device occurs, the handler defined above performs
//	 * the specific interrupt processing for the device.
//	 */
//	Status = XScuGic_Connect(IntcInstancePtr, TxIntrId,
//				(Xil_InterruptHandler)TxIntrHandler,
//				AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//		return Status;
//	}
//
//	Status = XScuGic_Connect(IntcInstancePtr, RxIntrId,
//				(Xil_InterruptHandler)RxIntrHandler,
//				AxiDmaPtr);
//	if (Status != XST_SUCCESS) {
//		return Status;
//	}
//
//	XScuGic_Enable(IntcInstancePtr, TxIntrId);
//	XScuGic_Enable(IntcInstancePtr, RxIntrId);
//
//
//#endif
//
//	/* Enable interrupts from the hardware */
//
//	Xil_ExceptionInit();
//	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
//			(Xil_ExceptionHandler)INTC_HANDLER,
//			(void *)IntcInstancePtr);
//
//	Xil_ExceptionEnable();
//
//	return XST_SUCCESS;
//}
//
///*****************************************************************************/
///**
//*
//* This function disables the interrupts for DMA engine.
//*
//* @param	IntcInstancePtr is the pointer to the INTC component instance
//* @param	TxIntrId is interrupt ID associated w/ DMA TX channel
//* @param	RxIntrId is interrupt ID associated w/ DMA RX channel
//*
//* @return	None.
//*
//* @note		None.
//*
//******************************************************************************/
//void DisableIntrSystem(INTC * IntcInstancePtr,
//					u16 TxIntrId, u16 RxIntrId)
//{
//#ifdef XPAR_INTC_0_DEVICE_ID
//	/* Disconnect the interrupts for the DMA TX and RX channels */
//	XIntc_Disconnect(IntcInstancePtr, TxIntrId);
//	XIntc_Disconnect(IntcInstancePtr, RxIntrId);
//#else
//	XScuGic_Disconnect(IntcInstancePtr, TxIntrId);
//	XScuGic_Disconnect(IntcInstancePtr, RxIntrId);
//#endif
//}
//
//
